State-of-the-art, high-speed integrated circuits necessitate advanced manufacturing and electronic circuit technologies capable of supporting systems that include tens or hundreds of millions of active devices. These rigorous system requirements are driven by market demands for ever-increasing system performance, feature sets, and system capabilities. Logic circuits fall into two broad categories: circuits that are clocked or synchronous, and circuits that are self-timed or asynchronous. Many circuit families exist for each of these broad circuit classifications. The logic circuit family that is chosen for a particular system design has a significant and direct impact on a variety of factors such as system performance, circuit density, power consumption, current leakage, and heat dissipation, among many other circuit parameters. Null convention logic (NCL) offers compact circuit layout, effective logic signal detection, and storage using asynchronous logic circuits.
Traditional digital logic circuits include logic elements which are continuously asserting a valid result, such as a logical “1” or a logical “0”. As new data is input to a traditional digital logic circuit, the result asserted by the circuit might change several times before stabilizing at the correct result. In a traditional digital logic circuit, the determination of completion can be accomplished by a reference outside of the logic circuit, such as a system clock. The external reference (e.g. system clock) can be used to indicate when the output of the circuit is in a valid state for evaluation. The system clock allows enforcement of the sufficient settling time for the logic circuit to stabilize at the correct result before declaring the output states to be valid and ready to be evaluated.
NCL differs from traditional digital (Boolean) logic, where each signal line may have one of two valid states. In traditional digital logic that uses a CMOS implementation, a low voltage level on a signal line means logical false or a “zero” value. A high voltage level on the same line means logical true or a “one” value. Thus a traditional digital logic signal may assume one of two values, both of which are valid.
NCL, however, includes a null state which has no meaning. For example, two separate signal lines can be used to convey two meaningful values. In this case, logic “false” would be conveyed by asserting a high voltage on the first line and a low voltage on the second line. Logic “true” can be conveyed by asserting a low voltage on the first line and a high voltage on the second line. A null state is conveyed by low voltage levels on both lines. Simultaneous high voltage levels on both lines are an invalid input state and are not used.
NCL has certain advantages over traditional digital logic. One such advantage is that the presence of a meaningful value at an NCL circuit output is sufficient to indicate that the circuit has completed intermediate logic operations and the output is valid for use by additional circuits. Therefore, with NCL, no external clock is required to indicate that output data is available for use. Nevertheless, as with any type of computation circuit, data integrity and validity are key components of an accurate and efficient logic evaluation system.